The present invention relates generally to high surface area capacitors for use in dynamic random access memories ("DRAMs"). More particularly, the invention relates to hybrid capacitors having trench and fin components.
In the on-going quest for greater memory density in DRAMs, various memory cell designs have been proposed. Much of the variation in such designs resides in the shape and location of capacitor plates in the memory cell. By way of example, capacitor designs that have been proposed (and in some cases commercialized) include stacked capacitors, spread stacked capacitors, trench capacitors, folded capacitors, and fin capacitors. Memory devices employing such capacitors are described in "Advanced Cell Structures for Dynamic RAMs" by Lu, IEEE Circuits and Devices Magazine, pp. 27-36 (1988); "A Spread Stacked Capacitor (SSC) Cell for 64 MBIT DRAMs" by Inoue et al., IEDM pp. 31-34 (1989); and "3-Dimensional Stacked Capacitor Cell for 16 M and 64 M DRAMs" by Ema et al., IEDM pp. 592-595 (1988).
Trench capacitors have found wide use in commercial high-density DRAMs. Trenches are particularly attractive because they utilize a substrate's third dimension (i.e., the direction normal to the substrate surface), and therefore occupy only very little area on the top surface of the substrate. While other capacitor structures can provide somewhat densely packed devices (e.g., planar and stacked capacitor devices), trench-based structures generally require even less chip area.
While trench capacitors provide space saving advantages, further improvements in device density may require capacitors of increasing storage capacity. This is because each trench capacitor of a DRAM must be capable of storing a certain minimum amount of charge in order to ensure that information is not lost between refresh cycles. Unfortunately, certain engineering obstacles have made it difficult to maintain a fixed level of storage capacity as device sizes and spacing between devices decrease.
The capacitance of a capacitor may be increased in three ways. First, as indicated above, it may be increased by increasing the surface area of the capacitor plates (e.g., the trench walls). Second, it may be increased by increasing the dielectric constant of an insulator separating the plates, and finally, it may be increased by reducing the thickness of the insulator. While some work has focused on engineering trench dielectrics to be thinner or have higher dielectric constants, such efforts are not particularly relevant to the invention described herein.
Some effort has focused on making narrow trench capacitors deeper so as to provide increased surface area. While this approach has yielded some improvements in device density, it is believed that to develop 64 megabit or greater trench-type DRAMs, trenches having submicron widths and aspect ratios of at least about 2.5 to 1 (depth to width) must be formed. However, trench capacitors in current 16 megabit DRAMs produced by Texas Instruments Corporation have widths of about 1.5 .mu.m and depths of only about 2.85 .mu.m. Unfortunately, available trench forming techniques have not yet proved able to reliably attain submicron trenches of the depth to width ratios necessary to reach the 64 megabit requirements.
Copending patent applications 08/531,727 entitled "INTEGRATED CIRCUIT DEVICE FABRICATION BY PLASMA ETCHING" and 08/531,473 entitled "INTEGRATED CIRCUIT DEVICE FABRICATION BY PLASMA ETCHING," and 8/531,659 "HIGH SURFACE AREA TRENCHES FOR AN INTEGRATED CIRCUIT DEVICE" all filed on Sep. 21, 1995, and naming M. Rostoker as inventor (all incorporated herein by reference for all purposes) describe improved techniques for forming high surface area trenches for use in trench capacitors. While such techniques represent improvements over the state of the art, it would be highly desirable have other capacitor designs for maintaining the capacitance of trench-type capacitors as device size and spacing decrease.